1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a guard ring, and more particularly to a semiconductor integrated circuit having a macro cell such as a hard macro or a large driving buffer.
2. Description of the Related Art
A guard ring is known as technique of protecting a macro cell such as a hard macro or a large driving buffer from noise. The guard ring is a diffusion region formed so as to surround the macro cell, and this diffusion region absorbs noise so that the macro cell is shielded from the noise.
A conventional guard ring used in a large driving buffer is formed, in the case the large driving buffer is composed of NMOS transistor, by disposing a p+ diffusion region so as to surround the large driving buffer on the outer circumference of the large driving buffer. At this time, the p+ diffusion region is provided in the p well, and a low potential power supply potential (VSS) is applied to the p+ diffusion region. On the other hand, in the case of the large driving buffer composed of PMOS transistor, an n+ diffusion region is disposed so as to surround the outer circumference of this large driving buffer. The n+ diffusion region is provided in the n well, and a high potential power supply potential (VDD) is applied to the n+ diffusion region.
FIG. 1A is a plan view showing a structure of a conventional semiconductor integrated circuit, and FIG. 1B is an enlarged plan view showing a part of a guard ring section 32 in FIG. 1A. As shown in FIG. 1A, in this semiconductor integrated circuit, a hard macro 31 is provided on a semiconductor substrate 30, and the guard ring section 32 is formed on the outer circumference of the hard macro 31 so as to surround the hard macro 31. The guard ring section 32 is intended to protect the hard macro 31 from noise.
The guard ring section 32 consists of double guard rings, and as shown in FIG. 1B, in an inside guard ring, an n well 33 is disposed in the surface layer of the semiconductor substrate 30, and an n+ diffusion region 34 is formed in the surface layer of the n well 33, while a VDD wiring 35 is provided on the n+ diffusion region 34. Further, between the n+ diffusion region 34 and VDD wiring 35, there are plural junctions 39a for connecting the n+ diffusion region 34 to the VDD wiring 35. In an outside guard ring, on the other hand, a p well 36 is formed in the surface layer of the semiconductor substrate 30, and a p+ diffusion region 37 is formed in the surface layer of the p well 36, while a VSS wiring 38 is provided on the p+ diffusion region 37, and moreover, between the p+ diffusion region 37 and VSS wiring 38, there are plural junctions 39b for connecting the p+ diffusion region 37 to the VSS wiring 38.
In these guard rings, each diffusion region absorbs noise, so that the macro cell such as hard macro or large driving buffer can be protected from the noise propagating in the well.
Furthermore, Japanese Patent Application Laid-open No. 62(1987)-73760 (hereinafter called cited reference 1) discloses an art of increasing the sink current by the guard ring. FIG. 2 is FIG. 3 given in cited reference 1, being a sectional view showing the operation of the carrier around the guard ring in the semiconductor integrated circuit in an embodiment in cited reference 1. In this semiconductor integrated circuit, an n well 46 is formed in the surface layer of a p type substrate 45, and a source-drain 41 of a p type FET (field effect transistor) is provided in the surface layer of the n well 46, while a p+ diffusion region 42 and an n+ diffusion region 43 are formed so as to contact with each other in the sequence closer to the source-drain 41, and further these diffusion regions are connected by a metal element 44. The p+ diffusion region 42 and n+ diffusion region 43 are formed so as to surround the outer circumference of the p type FET, and the metal element 44 is connected to the VDD power source (not shown). A guard ring 51 is composed of the p+ diffusion region 42, n+ diffusion region 43, and metal element 44.
FIG. 2 is a schematic diagram of behavior of carrier near the guard ring 51 when the guard ring 51 is in a completely floating state. Noise is applied to the source-drain 41. At this time, a current 47 is a parasitic bipolar collect current using the p type substrate 45 as the collector, a current 49 is a parasitic bipolar collect current using the p+ diffusion region 42 as the collector, and a current 48 is a base current accompanying the current 47 and the current 49. The current 49 passes into the p+ diffusion region 42 from the source-drain 41 with the holes as the carriers. A current 50 passes into the n+ diffusion region 43 with the electrons as the carriers. The holes, which are the carriers of the current 49, are re-coupled with the electrons, which are the carriers of the current 50, at the junction of the p+ diffusion region 42 and n+ diffusion region 43 and at the metal element 44. At this time, if the guard ring 51 is in floating state, by the current flowing in the p+ diffusion region 42, the metal element 44, the n+ diffusion region 43, and the n well 46, the potential of the p+ diffusion region 42 is almost kept at VDD, and the current 49 hardly decreases. Accordingly, it is effective to prevent change of potential of the p type substrate 45 due to the noise current applied to the source-drain 41 flowing into the p type substrate 45.
However, in the conventional guard ring, as mentioned above, although the noise propagating in the well can be shielded, the noise propagating through the power source wiring cannot be shielded. Recently, in the trend of higher integration and higher performance of semiconductor integrated circuits, the peak current is increasing, and the noise in the power source wiring tends to increase.
It is an object of the present invention to provide a semiconductor integrated circuit having a guard ring capable of effectively shielding the noise from the surrounding circuits and power source noise, and preventing malfunctions of the macro cell due to noise, without substantially changing the layout of the macro cell.
A semiconductor integrated circuit of the present invention comprises a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of the macro cell. The guard ring comprises an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well so as to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a second n+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied, a first p+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and a second p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied.
In the present invention, to achieve the object, diffusion capacitors are added to the guard rings disposed to surround the macro cell, such as the hard macro and the buffer of a large power consumption, that is, the large driving buffer. In other words, capacitors are formed between the n well and the first p+ diffusion region, and between the p well and the second n+ diffusion region. Accordingly, in the semiconductor integrated circuit, the capacitors are disposed so as to surround the macro cell. As a result, from these capacitors, an electric charge is released or supplied, and the electric charge is supplemented for charging and discharging of the wiring and through-current to the inverter, and it is effective to suppress voltage drop of the surrounding power source wire and voltage rise of the grounding wire. Hence, these capacitors can absorb steep power source noise caused by sudden change of the power source current to change the power source noise to a moderate one of small peak value, so that malfunctions of the macro cell can be prevented.
A semiconductor integrated circuit according to other aspect of the present invention comprises a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of the macro cell. The guard ring comprises an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well so as to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a second n+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied, and a first p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which a second potential lower than the first potential is applied.
Therefore, a capacitor can be formed between the p well and the second n+ diffusion region, and the power source noise is absorbed by the capacitor, thereby preventing malfunctions of the macro cell.
A semiconductor integrated circuit according to another aspect of the present invention comprises a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of the macro cell. The guard ring comprises an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well so as to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a first p+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and a second p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied.
Therefore, a capacitor can be formed between the n well and the first p+ diffusion region, and the power source noise is absorbed by the capacitor, thereby preventing malfunctions of the macro cell.
In the semiconductor integrated circuit, a first wiring may be connected to both of the first and second n+ diffusion regions to apply the first potential to the first and second n+ diffusion regions, and the first and second n+ diffusion regions may be disposed beneath the first wiring and parallel to the first wiring.
As a result, the layout size of the guard ring can be reduced, and the change from the layout of the conventional guard ring may be kept to a minimum limit.
As the macro cell, the hard macro or buffer can be used.